Problems which have to be overcome in fast MOSFET switching are discussed in “Gate Drive Characteristics and Requirements for HEXFET™ Power MOSFETs” International Rectifier Application Note AN-937, available from International Rectifier, 101 N Sepulveda Blvd., El Segundo, Calif. 90245, USA, which covers key requirements for driving MOSFETs.
An equivalent circuit of a practical MOSFET 10 is shown in FIG. 1. A package 20 for the MOSFET comprises a source with an internal source connection S, a drain with an internal drain connection D and a gate with an internal gate connection G and with a corresponding respective external source package terminal St, external drain package terminal Dt and external gate package terminal Gt. Under most conditions when driving MOSFETs three stray capacitances between the internal connections, a gate-source capacitance Cg_s, a drain-source capacitance Cd_s, and a gate-drain capacitance Cg_d, determine an ultimate switching speed of the MOSFET, for a given drive circuit and design.
However, MOSFETs are produced in a number of different styles of package 20 of which TO220 and TO247 are known examples. These packages require lead-outs to be taken from the MOSFET die 10 to the respective external package terminals St, Dt and Gt of the package 20. These lead-outs, however short they may be, produce a gate inductance Lg between the internal gate connection G and the external gate package terminal Gt, a drain inductance Ld between the internal drain connection D and the external drain package terminal Dt, and a source inductance Ls between the internal source connection S and the external source package terminal St which further affect the achievable switching speed. A gate resistance Rg also exists in series with the gate inductance between the internal gate connection G and the external gate terminal Gt. Connecting the device into a circuit may increase the effective magnitude of these inductances.
For the following reasons, the most significant of these stray inductances is the source inductance Ls. FIG. 2 shows a typical simple prior art circuit in which a gate drive circuit 21 is connected between the external source package terminal St and external gate package terminal Gt and a DC supply 22 is connected between the external source package terminal St and the external drain package terminal Dt. An external inductance Lext is present between the DC supply 22 and gate drive circuit 21 and the external source package terminal St. A drive resistance Rdrive is present between the gate drive circuit 21 and the external gate package terminal Gt. A load inductance Lload and load resistance Rload may be connected in series between the DC supply 22 and the external drain package terminal Dt.
During turn on, when a current Ids in the channel between the source and drain begins to rise, a voltage Vsource is induced across the source inductance Ls and the external inductance Lext between the external source packge terminal St and the gate drive circuit 21, where Vsource=(Ls+Lext)*d(Ids)/dt). This voltage opposes an effect of a voltage Vdrive from the gate drive circuit 21 and slows a switching speed of the MOSFET. Conversely, during turning off of the MOSFET, the Vsource voltage slows the turn off process. That is, whenever the source-drain current Ids is changing, a voltage is induced across the source inductance Ls and external inductance Lext that reduces the effectiveness of a drive voltage Vdrive applied to the external gate terminal. Moreover, power is predominantly dissipated from the MOSFET while the source to drain current is changing, so for this reason at least it is usually desirable to decrease the switching time.
Several manufacturers have produced packages that reduce the inductance Ls to very low values or provide separate terminals for a gate drive return to the source inductance Ls. An example of such a device is the IXYS DE475-102N21A, which incorporates both these features and is available from IXYS RF, 2401 Research Boulevard, Suite 108, Fort Collins, Colo., USA.
Other attempts have been made to increase switching speed in MOSFETs. For example, in “Hybrid MOSFET/driver for ultrafast switching” T. Tang and C. Burkhart Stamford Linear Accelerator Center Publication 13269, June 2008 (also published in Proc. IEEE International Power Modulators and High Voltage Conference, 27-31 May 2008, pp 128-130 and in IEEE Trans. on Dielectrics and Electrical Insulation 16(4), August 2009, pp 967-970) very high voltages of up to 30 V are used for the drive voltage Vdrive, switching between high positive voltages of +30V for turn on to large negative voltages of −30V for turn off. This is effective in increasing switching speed but is very stressful on the MOSFETs since it pushes the gate-source voltage to its very limit, usually only ±20V, and this can affect device life. Many drive circuit components are also required for implementation.
U.S. Pat. No. 5,332,938 proposes compensating for source lead inductance by adding a compensating inductor in parallel to the gate lead to supply an inductive voltage spike to the gate lead to form a more rectangular drive voltage waveform. However, this solution requires a gate drive current source and the insertion of a source resistance. For very high speed applications a physical size of the source resistance will add further inductance and provide a basic current limit to the final current as well.
WO 2007/137268 discloses a method of using a higher voltage to initiate current flow in the gate drive circuit using a pair of pre-charged capacitors charged to voltages which are high relative to the switching voltage rapidly to charge and discharge the gate and overcome a complex impedance of the gate drive circuit, the capacitors having sufficiently small capacitances that a maximum sustainable gate voltage is not exceeded.
WO 2005/025065 discloses a method of pre-charging an inductor in a resonant gate driver circuit before switching the device in order to improve the switching speed.
There is, however, a need to improve very fast switching performance of power MOSFETs with a minimum of additional components.